Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage
US9805803B2 · kind B2 · utility
1Cited by
2References
6Claims
0Family size
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Key dates
| Filing date | Aug 28, 2014 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Aug 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.