Co or Ni and Cu integration for small and large features in integrated circuits
US9805976B2 · kind B2 · utility
2Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Jan 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment of the present disclosure, a method for depositing metal in a feature on a workpiece is provided. The method includes electrochemically depositing a second metal layer on a first metal layer on a workpiece having at least two features of two different sizes in a dielectric layer, wherein the second metal layer is a copper layer and wherein the first metal layer includes a metal selected from the group consisting of cobalt and nickel, wherein the first metal layer completely fills the smallest feature but does not completely fill the largest feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.