Chip ID generation using physical unclonable function
US9811689B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Dec 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.