Read latency reduction in a memory device
US9812183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.