Memory cell with low reading voltages
US9812212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2017 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jan 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.