Thru-silicon-via structures
US9812359B2 · kind B2 · utility
4Cited by
7References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 8, 2015 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Jun 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes forming a first conductive diffusion barrier liner on an insulator layer within a thru-silicon-via of a wafer material. The method further includes forming a stress absorption layer on the first conductive diffusion barrier. The method further includes forming a second conductive diffusion barrier on the stress absorption layer. The method further includes forming a copper plate on the second conductive diffusion barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.