Nano-imprinted self-aligned multi-level processing method
US9812506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F2 3D cross-point memory array has been formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.