Memory control component with inter-rank skew tolerance
US9818463B2 · kind B2 · utility
8Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 26, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Dec 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.