Multi-die package comprising unit specific alignment and unit specific routing
US9818659B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.