Inventor · Scottsdale, AZ, US

Craig Bishop

33Patents
6h-index
14Co-inventors
66Inventor score

Filing activity: Oct 9, 1991 → Nov 20, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9040316B1 Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping Electricity 24 Active
US9177926B2 Semiconductor device and method comprising thickened redistribution layers Electricity 18 Active
US5249364A Front axle toe-in inspection process and apparatus Physics 15 Expired
US8656333B1 Integrated circuit package auto-routing Electricity 13 Active
US10050004B2 Fully molded peripheral package on package device Electricity 8 Active
US9576919B2 Semiconductor device and method comprising redistribution layers Electricity 7 Active
US9754835B2 Semiconductor device and method comprising redistribution layers Emerging Cross-Sectional Technologies 3 Active
US10056304B2 Automated optical inspection of unit specific patterning Emerging Cross-Sectional Technologies 3 Active
US9978655B2 Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping Electricity 3 Active
US9397069B2 Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping Electricity 2 Active
US11056453B2 Stackable fully molded semiconductor structure with vertical interconnects Electricity 2 Active
US9613830B2 Fully molded peripheral package on package device Electricity 2 Active
US9818659B2 Multi-die package comprising unit specific alignment and unit specific routing Electricity 2 Active
US9401313B2 Automated optical inspection of unit specific patterning Electricity 1 Active
US11444051B2 Fully molded semiconductor structure with face mounted passives and method of making the same Electricity 1 Active
US10157803B2 Semiconductor device and method of unit specific progressive alignment Electricity 1 Active
US11538759B2 Fully molded bridge interposer and method of making the same Electricity 0 Active
US12057373B2 Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects and method of making the same Electricity 0 Active
US11616003B2 Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Electricity 0 Active
US12170261B2 Molded direct contact interconnect structure without capture pads and method for the same Electricity 0 Active
US9520364B2 Front side package-level serialization for packages comprising unique identifiers Electricity 0 Active
US12381154B2 Fully molded bridge interposer and method of making the same Electricity 0 Active
US11887862B2 Method for redistribution layer (RDL) repair by mitigating at least one defect with a custom RDL Electricity 0 Active
US12424450B2 Embedded component interposer or substrate comprising displacement compensation traces (DCTs) and method of making the same Electricity 0 Active
US11728248B2 Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.