Semiconductor device isolation using an aligned diffusion and polysilicon field plate
US9818742B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2012 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Aug 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation structure prevents inter-device and intra-device leakage in first and second adjacent semiconductor devices in a substrate. The first and second semiconductor devices each include a gate region and at least one active region. A first channel stop region is configured to surround the first semiconductor device. A second channel stop region is configured to surround the second semiconductor device. A first field plate is located above at least part of the first channel stop region, and overlaps the gate region of the first semiconductor device in a first overlap region. A second field plate is located above at least part of the second channel stop region, and overlaps the gate region of the second semiconductor device in a second overlap region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.