Techniques for determining victim row addresses in a volatile memory
US9824754B2 · kind B2 · utility
2Cited by
1References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.