Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures
US9825185B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Dec 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.