Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor
US9825186B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.