Split gate embedded flash memory and method for forming the same
US9831087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates. The floating transistor gates are formed of charge storage material such as silicon nitride, Si3N4 in some embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.