Methods of forming MIS contact structures on transistor devices
US9831123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Apr 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.