Method for forming nanowires including multiple integrated devices with alternate channel materials
US9831131B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
Abstract
Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.