Patent · US Active

Programmable integrated circuit design flow using timing-driven pipeline analysis

US9836568B1 · kind B1 · utility

5Cited by

8References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Ilya K. Ganusov · San Jose, US
Aaron Ng · San Jose, US
Ronald E. Plyler · West Linn, US
Sabyasachi Das · San Jose, US
Frederic Revenu · San Carlos, US

Key dates

Filing date	Mar 14, 2016
Grant date	Dec 5, 2017
Priority date	—
Expiry date	Mar 19, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Improving timing of a circuit design may include determining, using a processor, critical feed-forward paths of the circuit design, determining, using the processor, a sequential loop having a largest loop delay within the circuit design, and iteratively cutting, using the processor, the critical feed-forward paths and feed-forward paths parallel to the cut critical feed-forward paths until a stopping condition is met. The stopping condition may be determined according to the largest loop delay. The circuit design may be modified by inserting a register at each cut feed-forward path.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.