Self-alignment of metal and via using selective deposition

US9837314B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Jeffrey Smith · Clifton Park, US
• Anton J. deVilliers · Boise, US

Key dates

• Filing date: Feb 2, 2017
• Grant date: Dec 5, 2017
• Expiry date: Feb 2, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.