Source-gate region architecture in a vertical power semiconductor device
US9837358B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.