Stacked complementary FETs featuring vertically stacked horizontal nanowires
US9837414B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6736
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After forming a stacked nanowire CMOS device including a first stacked nanowire array laterally surrounded by first epitaxial semiconductor regions, a second stacked nanowire array overlying the first stacked nanowire array and laterally surrounded by second epitaxial semiconductor regions, and a functional gate structure straddling over each semiconductor nanowire in the first and second stacked nanowire arrays, a common source/drain contact structure is formed on one side of the functional gate structure contacting one of the first epitaxial semiconductor regions and one of the second epitaxial semiconductor regions. A first local source/drain contact structure is formed on the opposite side of the functional gate structure contacting another of the first epitaxial semiconductor regions. After forming a trench isolation structure over the first local source/drain contact structure, a second local source/drain structure is formed overlying the first source/drain local contact structure and contacting another of the second epitaxial semiconductor regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.