Semiconductor device with split gate flash memory cell structure and method of manufacturing the same
US9837425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Apr 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.