Dual OTS memory cell selection means and method
US9837471B2 · kind B2 · utility
5Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Apr 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/24
Abstract
A 3D cross-point memory array includes a bitline and a word line. Both the bitline and the word line have multiple selector switches. Each switch of a corresponding bitline or word line is connected to a horizontal conductor or a vertical conductor so that a given bitline or word line has two switches, a horizontal conductor and a vertical conductor. By activating a particular horizontal conductor and vertical conductor, a specific bitline or word line is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.