Synchronized integrated metrology for overlay-shift reduction
US9841687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2015 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Feb 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.