Address translation cache that supports simultaneous invalidation of common context entries
US9842055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.