Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories
US9842642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2015 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Sep 17, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.