Patent · US Active

Method of manufacturing a semiconductor wafer having an SOI configuration

US9842762B1 · kind B1 · utility

0Cited by
2References
20Claims
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Key dates

Filing dateNov 11, 2016
Grant dateDec 12, 2017
Priority date
Expiry dateNov 11, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/31116
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.