Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above
US9842839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2017 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Jan 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.