Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices
US9842857B2 · kind B2 · utility
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28References
6Claims
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Key dates
| Filing date | Feb 23, 2017 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.