Electronic device including metal-insulator-semiconductor structure and method for fabricating the same
US9842881B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 1, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Nov 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.