Semiconductor wafer including a monocrystalline semiconductor layer spaced apart from a poly template layer
US9842899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2015 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Dec 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.