Self-aligned shallow trench isolation and doping for vertical fin transistors
US9842931B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.