Data transmission using delayed timing signals
US9843315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2012 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Jun 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.