Heterogeneous multiprocessor platform targeting programmable integrated circuits
US9846660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.