Stacked nanosheet field-effect transistor with diode isolation
US9847391B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2017 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Apr 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor. A substrate is provided that has a first conductivity type. A first semiconductor layer having a second conductivity type is formed on the substrate. A second semiconductor layer having the first conductivity type is formed on the first semiconductor layer. A field-effect transistor is formed that includes a fin having a plurality of nanosheet channel layers arranged in a vertical stack on the second semiconductor layer, and a gate structure wrapped about the nanosheet channel layers. The first semiconductor layer defines a first p-n junction with a portion of the substrate, and the second semiconductor layer defines a second p-n junction with the first semiconductor layer. The first p-n junction and the second p-n junction are arranged in vertical alignment with the gate structure and the nanosheet channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.