Method of using polysilicon as stop layer in a replacement metal gate process
US9847402B2 · kind B2 · utility
2Cited by
2References
7Claims
0Family size
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Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Aug 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.