Power gating based on cache dirtiness
US9851777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2014 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.