Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

US9852006B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Filipp A. Akopyan · Ithaca, US
• Rodrigo Alvarez-Icaza Rivera · San Jose, US
• John V. Arthur · Mountain View, US
• Andrew S. Cassidy · San Jose, US
• Bryan L. Jackson · Fremont, US
• Paul A. Merolla · Palo Alto, US
• Dharmendra S. Modha · San Jose, US
• Jun Sawada · Austin, US

Key dates

• Filing date: Mar 28, 2014
• Grant date: Dec 26, 2017
• Expiry date: Oct 27, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/063
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention relate to a neural network circuit comprising a memory block for maintaining neuronal data for multiple neurons, a scheduler for maintaining incoming firing events targeting the neurons, and a computational logic unit for updating the neuronal data for the neurons by processing the firing events. The network circuit further comprises at least one permutation logic unit enabling data exchange between the computational logic unit and at least one of the memory block and the scheduler. The network circuit further comprises a controller for controlling the computational logic unit, the memory block, the scheduler, and each permutation logic unit.