Method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell
US9852801B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Dec 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.