System and method in indium-gallium-arsenide channel height control for sub 7nm FinFET
US9852903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.