Patent · US Active

Superimposed transistors with auto-aligned active zone of the upper transistor

US9852950B2 · kind B2 · utility

0Cited by

2References

18Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Claire Fenouillet-Beranger · Grenoble, FR
Philippe Coronel · Barraux, FR

Key dates

Filing date	Jun 16, 2016
Grant date	Dec 26, 2017
Priority date	—
Expiry date	Jun 16, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Integrated circuit equipped with at least two levels of superimposed transistors, comprising:a first transistor at a first level,a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistora second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.