Memory device and method for fabricating the same
US9859290B1 · kind B1 · utility
9Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Nov 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.