Semiconductor device including a memory cell structure
US9859336B1 · kind B1 · utility
5Cited by
15References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 9, 2017 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Jan 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A semiconductor device including a memory cell structure is provided, and the memory cell structure includes an insulating layer disposed above a substrate, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode disposed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has a concave top surface lower than a flat upper surface of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.