Three-dimensional resistive memory
US9859338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Mar 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.