Integration methods to fabricate internal spacers for nanowire devices
US9859368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y40/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.