Semiconductor device with a passivation layer
US9859395B2 · kind B2 · utility
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4References
36Claims
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Key dates
| Filing date | Sep 30, 2014 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Mar 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.