Vertical field effect transistor with subway etch replacement metal gate
US9859421B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
Abstract
A method is presented for forming a vertical field effect transistor (VFET) structure. The method includes forming a plurality of vertical fins over a substrate, forming a dummy gate between the plurality of vertical fins, removing the dummy gate with a subway etch to define a gate cavity, and forming a high-k metal gate (HKMG) stack within the gate cavity. The method further includes forming the first and second source/drain regions before the HKMG stack. The method further includes defining the HKMG stack by a replacement metal gate (RMG) process, the RMG process defined in part by the subway etch. The subway etch enables removal of the dummy gate from a side portion of the VFET structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.