Performing read operations on a memory device
US9865357B1 · kind B1 · utility
1Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Dec 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.