Planarity-tolerant reworkable interconnect with integrated testing
US9865569B2 · kind B2 · utility
1Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Apr 25, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality of solder bumps, the plurality of protrusions includes sharp tips that penetrate the plurality of solder bumps, and a permanent electrical interconnection is established by physical contact between the plurality of protrusions and the plurality of solder bumps including a metallurgical joint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.