Contact array optimization for ESD devices
US9865584B1 · kind B1 · utility
1Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2016 |
| Grant date | Jan 9, 2018 |
| Priority date | — |
| Expiry date | Nov 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may be selectively modified in size, shape, placement and the like, to increase ESD protection performance, e.g., such as maximizing the transient current density, etc., in a standard ESD rating test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.